1. Field of the Invention
The present invention relates to a receiver of frequency-modulated signals with digital demodulator. The invention can be applied in all radio link systems.
2. Description of the Related Art
Frequency modulation or frequency shift keying is a technique commonly used to transmit a digital signal from a transmitter to a receiver by associating a particular modulation frequency with each digital value of the digital signal. In the case of a binary signal, a frequency f1 is assigned to the value 0 and a frequency f2 is assigned to the value 1. The transmitter has a modulator that sends out the modulation frequency associated with each digital value and the receiver has a digital demodulator responsible for restoring the binary values of the digital signal by discriminating between the modulation frequencies of the modulated signal received.
The demodulation of such signals consists, for example, in measuring the period of the signal received by sampling it at a very high frequency to detect the passages of the signal to zero and to compare the period value measured with period values corresponding to the different modulation frequencies. The precision of the measurement requires that the frequency of the sampling signal should be far higher than the modulation frequencies of the signal received. In other words, it should be far higher than the frequencies f1 and f2 in the case of a binary signal. The sampling frequency is then all the higher as the frequencies f1 and f2 are high. The sampling frequency must also be especially high when the frequencies f1 and f2 are close to each other so that the demodulator can accurately discriminate between them. Thus, in order avoid a situation where the sampling frequency needed is too high, the frequency of the received signal is generally lowered to an intermediate frequency of lower value by means of a frequency down conversion unit or frequency translation unit placed upline with respect to the digital demodulator in the receiver.
A receiver of this kind, referenced 10, is shown in FIG. 1. Generally, it has an antenna 11 to pick up a frequency shift keyed analog signal E(t), a first frequency translation unit 12 to lower the frequency of the signal E(t) and deliver a signal E′(t), a digital demodulator 13 to demodulate the signal E′(t) and deliver a digital signal N(t) representing the frequency-modulated signal E(t), and a clock circuit 23 to generate a high-frequency sampling signal ECH (with a frequency far higher than that of the signal E′(t) intended for the digital demodulator.
To lower the frequency of the signal E(t), the unit 12 has a local oscillator 14 that generates a local oscillator signal LO with a frequency fLO and a mixer circuit 15 that multiplies the signal E(t) with the signal LO. In this unit, the frequency of the signal E(t) is lowered by the value fLO.
The local oscillator 14 classically comprises a reference oscillator 16 delivering a reference signal REF and a phase-locked loop. The phase-locked loop comprises a two-input phase comparator 17 receiving the reference signal REF at a first input and a loop signal RT at a second input. The signal at output of the phase comparator 17 is filtered by a low-pass filter 18 and then processed by a voltage-controlled oscillator 19. The signal delivered by the voltage-controlled oscillator 19 is applied to the second input of the mixer circuit 15. It also has its frequency divided by a first frequency counter/divider 20. This counter/divider 20 divides the frequency of the signal LO by N or N+1 as a function of a control signal CMD (N is an integer). It delivers a signal CK whose frequency is itself divided by a second counter/divider 21. The signal coming from the counter/divider 21 is the loop signal RT that is applied to the second input of the phase comparator 17. A third counter/divider 22 is furthermore used to generate the control signal CMD. The counter/divider 22 receives the signal CK and a reset signal RAZ coming from the counter/divider 21. The counters/dividers 21 and 22 are presettable counters for which it is possible to modify the boundary value of the counting. In the example of FIG. 1, the counter/divider 21 is designed to count up to A and the counter/divider 22 up to B, with A>B. The working of this phase-locked loop is well known to those skilled in the art.
The counters 21 and 22 count the pulses of the signal CK. So long as the counter 22 has not reached the value B, the counter/divider 20 divides the frequency of the signal LO by N+1. It then divides the frequency of the signal LO by N until the counter 21 reaches the value A. The counter/divider 21 then resets the counter/divider 22 by means of the signal RAZ.
In the event of frequency shift keying with frequency hopping, the values A and B vary periodically and randomly in order to periodically modify the frequency of the signal LO.
A first aim of the invention is to optimize the size on silicon of such a receiver. This is why, according to the invention, it is sought to make a receiver that has no clock circuit to generate the sampling signal. Indeed, this clock circuit occupies a non-negligible surface on silicon. Furthermore, it consumes current and may create parasitic noises for the other elements of the receiver.
Another aim of the invention is to generate a precise measurement of the period of the signal E′(t).
Another aim of the invention is to propose a digital receiver that is simple in design.
According to the invention, means are provided in the local oscillator of the receiver and in the digital demodulator to compute the period of the lowered-frequency signal E′(t).
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.